The Linley Tech Processor Conference attracted 300 attendees.

In the first day’s sessions, one could easily get the impression that multicores are up to the task of network processing. Thanks to Mike Coward of RadiSys, however, the bold marketing claims got a good reality check. RadiSys build systems based on multicore technology. Today, they do 10G per line card. In two, years, they expect to run up to 100G, and 100G in a single chip is likely four years out, all according to his estimation.

For those that don’t want to wait this long, you are welcome to Xelerated. Our 100G wirespeed NPU is here, and now going into production. And in addition to any of the multicore processors in the market, it also includes an advanced traffic manager.

Update: Xelerated’s presentation on ‘Uncompromised throughput at low power’ can be found here.

Xpress: Were you nervous when you turned on the power on the first HX Rev B processor?

Johan Westergren: Excited is probably a better word for it. We have worked hard and made our preparation.

Xpress: How did the chip respond?

JW: We had an initial hick up, and yes, we got a bit nervous honestly. But it is very common that you set a parameter wrong. But once that was sorted, we could quickly move on to infrastructure tests. We ran BISTs on internal memories, we set clocks, and we ran basic functions on all subsystems. After the first business day, we had a multi- parallel test effort rolling.

Xpress: And what about the continuous progress?

JW: We work at a great pace and the chip behaves very well. We are keeping up with the test plan schedule.

Xpress: So what happens between now and product release in November?

JW: The test plan covers a range of cases, all of them well detailed, implemented and tested on the Rev A version of the HX network processor. System test run application scenarios to verify the chip against customer application types. In addition we have started characterization to validate how the chip behaves under different power and temp conditions.

Xpress: Can you say anything on the quality?

JW: This far it looks promising. We pay close attention to quality in the architecture and design of the chip, and it is in the testing environment you see how that starts to pay off.

Read all about the family of HX network processors, and the Carrier Ethernet solutions they empower.

So, let us look at an example of a 100GE board of today, using in-house designed packet processing silicon:

The line card is packed with silicon to perform packet processing, traffic management and buffering for 100 Gbit/s of traffic. Here is where the new member of the HX family, the HX336 comes into play. The HX336 includes a 100 Gbit/s traffic manager with deep packet buffering in off-chip DRAM. By utilizing the service density of the HX family, the line card above can be optmized to only use two chips for packet processing and traffic management, a pair of HX326 and HX336. The HX336 is used in the egress pass supporting both packet processing and traffic management. The HX326 is responsible for traffic classification and packet processing in the ingress path. Reducing the number of chips for packet processing, traffic management and buffering from four to six to two result in significant power and cost savings. Several of our customers have witnessed a 50% reduction of power consumption.

The new HX336 network processor is Xelerated’s contribution to the industry’s transition to 100GE and optical transport networks OTU4 standard. The transition may not be immediate, but as technologies matures, the shift may be stronger than expected.

While 100GE is still in trial phase, large-scale backbones and data centers are now hitting the limits of the 10GE technology. The demands for merchant 100GE optics and network packet processing are required to enable the technology shift.

While analyst firm Infonetics projects a mass-market for 100GE in 2015, the demand is here and now. Let’s put in another gear to shorten the time to the 100 GE mass-market.

For all those who didn’t get to see the demo, I recommend watching the video demo we conducted with Brian Fuller of EE Times.

Per Lembre demonstrates 100G

Over four weeks, we are visiting 40 customers and partners to demonstrate our new technology.  Many of them have said this is the first time they have actually experienced a demonstration of wirespeed processing at 100G in a single chip.

Here are some of my reflections this far:

• 100G is hot. With the finalization of the 100GE and 40GE standards, there is a huge interest to scale packet processing to the next level. 100G wirespeed network processors that can match the new step in link capacity will be critical to the commercial success of 100GE.
• Greater port densities in next generation fiber access systems. Xelerated’s OLT and unified fiber access customers are pushing to get the next generation systems to market as soon as possible. Service providers, primarily in Asia, are driving the need for more bandwidth and customized features to fit local market conditions.
• Power reduction is critical. In several meetings, our customers indicated that the HX and AX technology can reduce the power consumption with more than 50% compared to a competitive solutions. This has implications for both the environment and the operational cost of running the networks. Reduction in power consumption also enables new types of designs that are more efficient and require a smaller footprint.
• Wirespeed by Design. We use this term as a tag line for the company.  Through these meetings, I now realize just how well it resonates with our customer base. The dataflow architecture enables wirespeed packet processing without degradation when all services are turned on. It simplifies engineering, and our customers gain time to market. In addition, they are assured the products will come out well in performance tests.

The demo tour marks an important milestone for many of our customer design projects. The huge increase in demand on Reference Design Kits and the intensive customer correspondence on technical requirements are two safe signs of what’s ahead of us. It will be a lot of work, and a lot of fun!

By the way, we invited Craig Matsumoto at Light Reading to see the world’s first 100G demo. It all went very well, as expected, however there was initial confusion about bitrates and packet rates for 100Gbps Ethernet wirespeed. Please refer to the comment section to the blog post for more details.

This is the formal start of next generation Ethernet innovation. This is good news for the industry, and well supported by us here at Xelerated.